Multi chip package for mobile communication devices

A primary logic die comprising through silicon via (TSV) connections and a second die (eg a memory) or a decoupling capacitor may be embedded in the plurality of build-up layers. An electrical path may be defined in the build-up layers of the device package to route electrical power or a ground signals between the second die or capacitor and the electrical routing features, bypassing the through silicon via connections of the primary logic die. The requirement for the number of TSVs in the logic dies are reduced, allowing die sizes, utilisation of die area and package size to be optimised to provided a small package size.