Divider-less locked loop circuit providing non-integer multiples of a clock signal

A locked loop circuit 10 comprises a reference clock signal input 12, a VCO 18, and a delay cell 14 which is arranged to apply a delay to the reference clock signal in accordance with a saw-tooth pattern (fig.2). The locked loop circuit 10 also comprises a phase comparator 16 arranged to compare the phase of the delayed clock and the output of the VCO, and an integrator 20 arranged to integrate the output of the comparator and to provide a signal to control the VCO. The locked loop circuit 10 further comprises a feedback circuit arranged to measure the phase comparison signal at a wrap point of the saw-tooth pattern and to control the amplitude of the saw-tooth pattern in dependence thereon. The ramping saw-tooth signal may cause an incrementally changing delay and thus shift the VCO to a new, constant frequency; modulation 30 may also be applied. The invention removes the need for a conventional, power-hungry, feedback divider in a locked loop circuit and provides a range of output frequencies not necessarily equal to an integer multiple of the input clock.