Memory interface with a clock channel, command bus and address bus

Disclosed is a dynamic random access memory (DRAM) interface 214. The DRAM interface includes a channel for a differential clock signal 312, an un-calibrated parallel command bus 314, and a high-speed, serial address bus 316. The address bus may be calibrated after power up using a link training rou...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BARRY A WAGNER, ALOK GUPTA
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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