Memory interface with a clock channel, command bus and address bus

Disclosed is a dynamic random access memory (DRAM) interface 214. The DRAM interface includes a channel for a differential clock signal 312, an un-calibrated parallel command bus 314, and a high-speed, serial address bus 316. The address bus may be calibrated after power up using a link training routine, which may include transmitting via the parallel command bus a first command to indicate that a sequence of training patterns are to be sent to the memory via the serial address bus. The memory stores the received versions of the sequence of training patterns in link training registers. The interface then reads the values stored in the link training registers via the data bus and based on the values read from the registers determine transmission parameters associated with the address bus. The memory may have a plurality of DRAM modules each coupled to a logic device which coupled to the interface, the logic device configured transmit commands and address to the appropriate module.