A field Effect Transistor with a plurality of Inactive Gate Channels

A field effect transistor (FET) 1 comprising a semiconductor substrate 2 comprising an electrically conducting channel layer 3 therein. A plurality of source and drain fingers 4, 5 which may be interdigitated are arranged on a first face of the substrate, each finger separated from the adjacent finger by a gate channel 6. The gate channels 6 comprise at least one active gate channel 6b defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer. There are a plurality of inactive gate channels 6a are defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer. The gate channels are arranged such that each active gate channel has a gate channel on each side. Each active gate channel comprises a gate 7 therein for controlling current flow in the electrically conducting channel layer. A method for manufacturing the FET 1 using resist is also disclosed.