Method and system for verification of microprocessor designs with multiple power gate domains

The invention relates to a method and a system for verifying a microprocessor design with multiple power gate domains (21, 22). The checks are done via structural checks of a hierarchical netlist of the design and use signal based traversion. Specifically, the invention encompasses an identification of the power gate domains (21, 22) within the design, defining traversal trajectories along signal interconnections (61, 61', 61'') between power gate domains (21, 22) and determining compliance of interconnections between starting points (71. 71', 71'') and end points (72, 72', 72'') of said trajectories with respect to a set of design rules.