Hierarchical memory correction system and method

A hierarchical error correction system and method operable with a computer memory system (300). In one embodiment, the memory system (300) comprises a plurality of memory modules (108-1 to 108-N) organized as a number of error correction code (ECC) domains, wherein each ECC domain (400) includes a set of memory modules (402A, 402B), each memory module comprising a plurality of memory devices. A first error correction engine (106/305A) is provided for correcting device-level errors such as single and multibit errors, for example by chip-kill. A second error correction engine (106/305B) for correcting errors at a memory module level, wherein the first and second error correction engines (106/305A, 106/305A) are operable in association with a memory controller (104/302) operably coupled to the plurality of memory modules (108-1 to 108-N). Redundancy, crc and parity methods are employed in embodiments.