Detecting a malfunctioning host coupled to a communications bus

A computer system 220 includes a processor 102a coupled over a local bus 104a to a master bus transceiver 256a. Bus transceiver 256a is coupled over communications bus 108 to other slave bus transceivers 256b, 256c. Watchdog timer 260a is coupled between processor 102a and transceiver 256a. The Watchdog timer 260a includes a failure detector 262a for determining if processor 102a has failed. If processor 102a fails, the failure detector 262a transmits a failure indication 266 to master transceiver 256a. In response the master transceiver 256a broadcasts a failure message 272 over the communications bus 108 to the slave transceivers 256b, 256c and relinquishes control or ownership of the bus 108. The bus transceivers 256b, 256c may suspend communication with transceiver 256a and, thus, avoid hanging the communications bus 108. A byte timer 278a may be used to determine whether the processor 102a has failed.