Capacitor for a semiconductor device and method of manufacture

A capacitor 25 is formed entirely within a metallization layer of a damascene interconnect structure which includes a semiconductor device 16. A trench (fig 2: 22) is formed in the dielectric material of the metallization layer (fig 2:13). A first capacitor electrode 26 is formed within the recess in electrical contact with the component 16 in the layer. An insulator layer 30 is formed over the first electrode, then a second capacitor electrode 27 is formed over the insulator layer. The capacitor layers are conformally deposited within the trench. A second device component may be placed in electrical contact with the second electrode.