Multiple dispatch processor architecture with resource allocation

A multiple dispatch processor has several instruction fetch units 202, 204, each for providing a stream of instructions to an instruction decode and dispatch unit 206, 208. The processor also has a resource allocation unit 210, and multiple resources such as combined integer and address execution pi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ERIC S FETZER, WAYNE D KEVER, ERIC R DELANO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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