Multiple dispatch processor architecture with resource allocation

A multiple dispatch processor has several instruction fetch units 202, 204, each for providing a stream of instructions to an instruction decode and dispatch unit 206, 208. The processor also has a resource allocation unit 210, and multiple resources such as combined integer and address execution pipelines 220 and floating point execution pipelines 222. Each instruction decode and dispatch unit 206, 208 requests resources needed to perform an instruction of the resource allocation unit 210, which arbitrates among the multiple instruction decode and dispatch units. The resource allocation unit 210 grants available resources to the instruction decode and dispatch units 206, 208 according to their needs and, in a particular embodiment, according to their relative priorities.