Parallel cyclic redundancy checking with last segment padding

Apparatus for performing a cyclic redundancy code check on a binary digital signal consisting of a variable multiplicity (M) of data bytes comprises a buffer register for temporarily storing in succession segments each consisting of an integral number (N) of bytes. Each successive segment is loaded into a cyclic redundancy checker which produces a remainder after performing polynomial division of the digital signal. When the number of bytes of the digital signal in the last segment is less than said integral plurality (N) that last segment is padded with constant data. The signal is deemed valid if the said remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with zero to (N-1) bytes of the constant data. For speed, each segment is deserialised and loaded into the checker as parallel data.