Measuring bit error rate (BER) in multiple data channels and control channel selection

A high speed link between chips (1,2) and comprising a multiplicity of synchronous serial data channels (5) includes an onboard detector (10) for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having t...

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Bibliographische Detailangaben
Hauptverfasser: MARK HUGHES, NOEL J BUTLER, UNA QUINLAN, EUGENE O'NEILL, NEIL OLIVER FANNING
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A high speed link between chips (1,2) and comprising a multiplicity of synchronous serial data channels (5) includes an onboard detector (10) for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest data rate as the control channel and optionally to render at least the channel with the highest data rate inactive.