Dynamically setting latency values for memory access

Computer processor 10 includes a dynamic latency module 12, including a read-only memory (36, Fig. 2) which stores a plurality of sets of latency values, each value indicating the time delay, in number of clock cycles, appropriate for a type of processor access operation to memory such as cache 20. A routine, which may be part of the BIOS code of the computer system 16, is executed (Fig. 3) which determines which set of latency values is appropriate for the particular processor, by determining the processor's actual operating speed, e.g. by multiplying the measured speed of external bus 25 with an operating speed multiplier. A latency index corresponding to the operating speed is used to retrieve the appropriate set of latency values from ROM (36, Fig. 2). The latency values are placed in a register (34, Fig. 2) and used by the control logic (32, Fig. 2) when the processor 10 accesses the memory 20. If the processor is operating at a slower-than-rated speed, the latency values are thus correspondingly decreased so that the processor operates more efficiently. Latency fuses 14 can be set to override the dynamically set latency values.