Merged memory and logic (mml) intergrated circuits including independant memory bank signals

A merged memory and logic (MML) integrated circuit includes a memory block having a plurality of memory banks, each of which is independently controlled by row address strobe signals, column address strobe signals and write enable signals. A logic block is connected to the memory block and generates an independent row address strobe signal, column address strobe signal and write enable signal for each of the plurality of memory banks. The memory block may also comprise a controller that independently controls each of the memory banks. The controller is connected between the logic block and the plurality of memory banks to receive the independent row address strobe signal, column address strobe signal and write enable signal for each of the plurality of memory banks from the logic block. Accordingly, high speed operation and control of memory banks in an MML integrated circuit may be provided. The MML integrated circuit also includes a test signal input/output unit that transmits external test signals from external to the MML integrated circuit to the memory block during testing of the MML integrated circuit, and that receives tests that are generated by the memory block during testing of the MML integrated circuit for transmission external to the MML integrated circuit.