Expanded I/O address space

Expanded I/O address space

An information processing system includes a processor (12) having a circuit for omitting input/output (I/O) address signals within a predetermined n-bit I/O address range, and apparatus (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BECHARA BOURY, RONALD VALLI, JOHN WILEY BLACKLEDGE
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An information processing system includes a processor (12) having a circuit for omitting input/output (I/O) address signals within a predetermined n-bit I/O address range, and apparatus (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor, to provide an expanded I/O address space. A bus bridge (Fig. 4) is also described. If the high bits of an address fall within a predetermined range then the low bits are transmitted to another bus.