Methods of forming an interconnect on a semiconductor substrate

In a method of forming an interconnect channel within a. semiconductor device, a first dielectric layer 22, 23 is deposited over a semiconductor substrate 20 and patterned to form a contact opening that is subsequently filled with a contact plug 40, 41. A second dielectric layer 50 is deposited over...

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Bibliographische Detailangaben
Hauptverfasser: DONALD S GARDNER, XIAOUN MU, SRINIVASAN SIVARAM, DAVID B FRASER
Format: Patent
Sprache:eng
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Zusammenfassung:In a method of forming an interconnect channel within a. semiconductor device, a first dielectric layer 22, 23 is deposited over a semiconductor substrate 20 and patterned to form a contact opening that is subsequently filled with a contact plug 40, 41. A second dielectric layer 50 is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer 50 is patterned to form the interconnect channel, wherein the first dielectric layer 22, 23 acts as an etch stop to prevent etching of the substrate. A metal layer 61 is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect channel. The first dielectric layer may be of BPSG and silicon nitride 23 which acts as the etch atop. The contact plug is of tungsten within a diffusion barrier 40 of titanium nitride. The second dielectric layer 50 is of silicon dioxide end the interconnect metal 61 is of copper. Further layers of similar construction end materials may be added to provide a multi-level interconnect construction.