INTERFACE CHIP FOR A VOICE PROCESSING SYSTEM

An interface chip 10 is capable of receiving requests from two processors via busses 32,13 and coordinating the flow of the data therebetween. The chip 10 comprises interface units 26, 12, with a plurality of ports, an arbitration unit (state machine) 16, a control register 14, a DRAM interface 20 and a timing unit (clock) 24. The chip functions as a dual port controller for interaction of associated RAMs and processors of a voice processing system. The several interface circuits are in communication with a host computer via bus 32 for the purpose of accepting requests in sequence and outputting data over a bus. The host computer is in communication with a RAM interface 20 of each chip that interfaces a local peripheral board processor (not shown) through a dual port RAM which resides on the peripheral board.