Two-step subranging analog to digital converter

A subranging analog-to-digital converter (ADC) that comprises a biasing architecture including a single string of transistor current sources used to generate the reference digital-to-analog converter (DAC) bit currents, the low-resolution flash ADC reference ladder voltage, and the ADC bipolar offset voltage. The reference DAC resistors, low resolution voltage reference ladder resistors, error amplifier gain set resistors, and the bipolar offset resistors are all constructed from the same material and using the same physical construction, so that they match with high precision and track over process and temperature. In one embodiment, the low-resolution flash ADC is itself implemented as a two-step parallel subranging ADC, comprising a most-significant-bit reference ladder and a least-significant-bit reference ladder, and includes an internal flash DAC whose bit currents are also provided by the same single string of transistor current sources. In addition, a shunt resistor across the least-significant-bit reference ladder of the low-resolution flash ADC makes it possible to tie it in series directly to its most-significant-bit reference ladder using the same resistor material, thus providing inherent tracking of the reference voltages of the two ladders. Finally, a bias current compensation resistor network is provided on the input side of the flash ADC comparators to cancel input bias current errors.