Digital data separator

A data separator produces a reference clock from encoded data through the use of digital logic that simulates the operation of an analog phase-locked loop. The digital phase-locked loop includes a counter oscillator (14) that develops a period value which is incrementally modified in accordance with time variations in the input data to maintain the regenerated data in proper phase relationship with the clock. The counter oscillator comprises a zero-crossing counter which supplies a reference clock signal (EC) to a clock and data regeneration circuit (16). The counter is incremented until its count is equal to the previously computed normal period value. The counter is latched by a synchronized input data pulse (SYNCDT) and the latched value represents the required period adjustment. As the data is synchronized with the reference clock the value of this adjustment (DBUS) approaches zero. The circuit also includes a digital low-pass filter (18) that comprises a memory element that allows the new phase correction data to be added to the time-weighted previous period data.