Output buffer precharge circuit for DRAM

The output line Dout of output buffer 5 of a DRAM is precharged to either a high, or a low logic level to reduce the time required to charge or discharge the output line on reading out the memory. Control precharge pulse generator 10 produces a control precharge pulse DCPP on detecting an address transition signal ATS. The pulse DCPP is used, in conjunction with the data on data lines DB, DB to produce a pulse D1P or D0P to switch on either M6 or M5 respectively to discharge or charge the output line Dout in advance of read out occurring.