DIGITAL DATA SEPARATOR

A data separator produces a reference clock from encoded data through the use of a digital logic that simulates the operation of an analog phase-locked loop. The digital phase-locked loop includes a counter oscillator that develops a period value which is incrementally modified in accordance with time variations in the new input data to maintain the regenerated data in proper phase relationship with the clock. The counter oscillator includes a zero-crossing counter which produces a reference clock signal to a clock and data regeneration circuit. The counter is incremented until its count is equal to the previously computed normal period value. This counter value is latched by a syncronized input data and represents the required period adjustment. As the data is syncronized with the reference clock the value of this adjustment approaches zero. The circuit also includes a digital low-pass filter that comprises a memory element that allows the new phase correction data to be added to the time-weighted previous period data.