Frequency divider circuits

A frequency divider circuit allows a desired long-term output frequency (with acceptable short-term deviations) to be generated from a master crystal oscillating at a higher frequency. A digital monostable divider unit D1 is connected in cascade with another such unit D2 and is supplied with a stable oscillator-controlled frequency input at I. The unit D1 has a period of N cycles, providing the major frequency division component, and the unit D2 provides the desired lower output frequency at O and is controllable for alternative switching after 1 or 3 cycles instead of the normal 2, the sum of the periods (N+2) representing the basic division ratio of the circuit. The output O is connected to the input i of a digital M counter which resets automatically after a count of M, when an output "modify" signal from an output o of the counter is applied at m to the divider unit D2. This signal renders operative a control signal applied to a fast/slow control signal input c1 of the unit D2 so that this unit switches after 1 or 3 cycles, instead of the basic 2, according to the value of the control signal. The M counter is programmable by a programme control signal at c2, so that the value of M can be varied to vary the long-term output frequency.