Majority decision ULA theta

A majority decision logic circuit uses a semiconductor ULA theta , and has four triplicated channels one of which is a clock channel (channel A) while the other three (channels B, C and D) are signal channels. Each channel has triplicated, and nominally identical, inputs and in each channel the circuitry derives from the triplicated inputs a majority vote output, and these majority vote outputs are the circuit's outputs. Each channel also has a majority vote input, either the internally generated majority vote or an external majority vote, and within each channel its majority decision vote is compared with the triplicated inputs. Hence if a fault occurs, the output due to that fault also causes the faulty channel's inputs to be compared with the majority vote to identify which level within the channel is at fault. An output selection circuit enables a faulty channel's outputs to be monitored to given an indication as to which channel and which level is faulty. Alternatively all the channels can be polled so that their fault/no fault states are continuously monitored.