Circuit for interfacing a processor to a line circuit

A line switch for a digital telephone switching system which uses distributed processing, has one or more switch modules, 1a, 1b, each coupled to a central office switching system via one or more PCM lines PCMA, PCMB using common channel signalling. Each module comprises groups of line circuits 11, each coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor communicates with the central office switching system and coordinates the operations within the line switch module. A second processor controls clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch. Communication between the processors is via common buses carrying TDM-PCM data and control data. A standardised interface circuit is provided which interfaces each line circuit to the third processor and also to the busing arrangement.