MICROPROCESSOR WITH MEMORY HAVING INTERLEAVED ADDRESS INPUTS AND INTERLEAVED INSTRUCTION AND DATA OUTPUTS
A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation. |
|---|