IMPROVEMENTS IN OR RELATING TO COMMUNICATION SYSTEMS

1,218,581. Automatic exchange systems; multiplex pulse code signalling. WESTERN ELECTRIC CO. Inc. 4 April, 1968 [6 April, 1967; 9 Oct., 1967], No. 16240/68. Headings H4K and H4L. In a TDM communication system utilizing delta modulation, the duration of each frame (exchange cycle) is proportional to the number of active stations. A recirculating type memory contains the address of each pair of stations in communication (separate time slots are used for Go and Return signals) and on the appearance of each pair of addresses the corresponding stations are interrogated to determine whether or not a delta modulation " 1 " bit viz a positive change in amplitude of a speech signal, is present. If there is a " 1 " bit; the cycle is interrupted for 10 nanoseconds so that this bit can be transferred between the stations. If a " 0 " bit viz. a negative change in amplitude of a speech signal, is present, however, the cycle is not interrupted and at the end of the 3 nanosecond interrogation period the next pair of addresses are retrieved. Transmission quality increases with a decrease in the number of active stations due to,the increased sampling rate. Particular description, first embodiment, Fig. 2. - It is assumed that stations 10 and 10n are in communication and that their addresses are written in two time slots in memory 15. It should be remembered that a time slot is 3 nsecs. long for a non-talking station and 10 nsecs. long for a talking station. In one time slot (Go) the address of station 10's transmitter 11 is written in the codes address side of memory 15 and the address of station 10n's receiver 12n is written in the decoder address side of the memory. In the other time slot-which is not necessarily adjacent to the first slot-the address of 10n's transmitter 11n and 10's receiver 12 are written in the coder and decoder sides.respectively of the memory. In response to the simultaneous appearance of the addresses 11, 12n from the memory and provided that a delta " 1 " bit is present at the output of 10's transmitter 11, then AND gates 160 and 161n are opened to "convey" " this bit to 10n's receiver 12n. A monopulser 163 causes a 1‹ nsec. delay between the openings of the two gates and also steps the memory on via OR gate 169. However, if, in the same time slot (viz. addresses 11, 12n present) a " 0 " bit had been present at 11's output, then gate 160 would not have been opened and hence monopulses 163 and gate 161n would not become operative. However, inverter