MULTI-PROGRAM DATA PROCESSOR

1,202,452. Data processing systems. BURROUGHS CORP. 18 June, 1968 [19 June, 1967], No. 28883/68. Headings G4A and G4C. In a multiprogramme data processing system comprising an addressable memory having a plurality of queues of instructions stored therein and waiting to be executed, each of said instructions being stored in a separate memory location together with a link address which serially links the instruction to another in the respective queue, means are provided and separately claimed for respectively adding a new instruction to a queue utilizing a tail address of a queue stored with a current instruction and for accessing the first instruction of a queue to form a new current instruction utilizing a head address of a queue stored with a current instruction. As shown (Figs. 1 and 3) a data processing system comprises a data processor 100 including a magnetic core working memory 102 in which said queues are formed. Instructions are stored in memory 102 in random order but each instruction includes a link address pointing to the next instruction in the queue. A common list control 520 maintains a list of spare memory locations. The data processing system also includes a magnetic disc storage unit 200, associated control unit 300 and a distributer memory system 400 comprising a magnetic core memory 404 for storing disc access instructions in locations corresponding to the sectors to be accessed. If more than one instruction exists for any one sector a queue is formed in the memory 102 under control of a queue control 600 (shown in detail in Fig. 3). A queue is formed for each of the multiple programmes being processed by the processor 100 and for each disc sector for which multiple access instructions exist. A programme analyser 500 receives instructions from the disc unit and converts them either into data processing instructions which are passed to the processor 100 (register 108) or into disc file instructions which are passed to the distributer memory system (register 402). Each current instruction in the distributer memory 404 and the processor instruction register 104 includes the address of the head and the tail of the corresponding queue. Obtaining a new current instruction from a queue.-Whenever an instruction is selected for execution by the disc control unit as the corresponding sector becomes available for reading or writing, a control signal RQd is produced by a signal generator 414 as a result of which the old current instruction is gated