Improvements in or relating to Digit Storage and Transmission Means

1,195,141. Impulse transmitters. TELEPHONE MFG. CO. Ltd. 20 Dec., 1968 [2 Jan., 1968], No. 282/68. Heading H4K. [Also in Division G4] The invention relates to a means controlling writing in and reading from a digital data memory and is particularly for use in telephone systems to provide dialling pulses having a predetermined gap between signals indicative of a particular digit and a larger predetermined gap between consecutive digits. Removal of a telephone handset causes resetting of all circuits via delay DC and reset circuit RS and a key pressed on the handset causes a decimal to binary coded decimal converter to produce a signal applied to AND gate SAG (Fig. 1, not shown) enabled whenever a key is pressed to set flip-flop MC1 to overcome discrepancies that may otherwise be produced by contact bounce. The flip-flop supplies a signal to AND gate ISC enabled by a single pulse recirculating in a 16- stage shift register ISG. A pulse from DSC enables AND gate AG2 and inhibits AND gate AG1 via inverter I1 to cause the circulating pulse to be delayed by one stage. The pulse from ISC also enables AND gates IAG1-IAG4 to supply the B.C.D. number to recirculating memories BSL-4. A 16-stage shift register OSG contains a pulse initially recirculating in synchronism with the pulse in ISG but due to the extra delay provided by BD1 is now one stage ahead of the pulse in ISG. Coincidence of the pulse in OSG, absence of the pulse in ISG and a signal indicating that a counter CTR-O enables AND gate OSC to supply a signal I3 causing the pulse in OSG to be delayed one stage by BD2 and causing readout of the signal from memories BS1-BS4 via AND gates OAG1- OAG4 and preventing regeneration via AND gates CAG1-CAG4 and storage of the number in the counter CTR. A clock pulse generator CG produces pulses of frequency 30 KHz which are divided by scale of ten counters DC1-DC3 to produce pulses of 30 per second. These are passed by AND gate AG7, divided by 3 and then used to count down the counter CTR to produce a series of pulses at the rate of 10 per second equal in number to the number stored in the counter. The OSC signal causing readout of the data from memories BS1-BS4 also sets flip-flop BC2 to enable AND gate AG6 to apply a 30 Hz signal to unit PD causing division by 24. The OSC signal also sets flip-flop BC3 which is reset by the divided signal causing a gap of 0À8 seconds between consecutive digits read out before AND gate AG7 can be enabled. The units are preferably Fie