Selection Circuit

1,186,704. Transistor switching circuits. INTERNATIONAL BUSINESS MACHINES CORP. 1 March, 1968, No. 9989/68. Heading H3T. [Also in Division G4] In a selection circuit for selecting from an ordered set of electronic components, the next operable component to a component issuing a selection signal, a series-connected chain of impedances is provided with selection signal sense circuits of successive components of the set connected to successive nodes of the chain and a selection signal generator of each component connected to the same node as the sense circuit of the next component of the set, the sense circuit of each inoperable component presenting to a selection signal an impedance substantially greater than that of any impedance of the chain. Word storage locations W0, W1, W2 ... (Fig. 1) of an associative store have respective selector triggers (not shown) to control which locations participate in read and write operations. A " NEXT " operation causes any selector trigger, which is set, to energize the corresponding line 2 and set the selector trigger of the next non-defective word storage location via a generating circuit G, resistor chain R1, R2 ..., a sense circuit S, an AND gate 4 and a transfer trigger (not shown). Fig. 2 shows a generating circuit G(N) comprising long-tailed NPN transistor pair T1, T2, and a sense circuit S(N+ 1) comprising transistor T3, regulating transistor T4 and clamp circuit T5, T6. The sense circuit of a defective word storage location has had its disconnection switches D opened (or fuses blown) previously so the sense circuit presents a high impedance to the resistor chain R1, R2 ... and so is skipped. Each resistor R1, R2 ... may be replaced by two equal resistors in series, with their common terminal clamped. In this case the inverters I of Fig. 1 may be dispensed with so each word storage location can accept a signal through S and AND gate 4 and deliver one through G simultaneously. Each resistor in the chain can be replaced by a diode or a plurality of diodes in parallel. The invention can also be used for skipping defective packages in a series of packages of integrated circuitry used in turn for processing data.