Bi-phase asynchronous frame decoding process for use in electronic circuit, involves detecting length in relevant bits of bi-phase asynchronous frame to decode frame, and selecting functioning mode of electronic circuit

The process involves detecting a length in relevant bits of a bi-phase asynchronous frame to decode the frame, where the length of the frame varies from one frame to another frame. A functioning mode e.g. normal mode and test mode, of an electronic circuit is selected based on the detected length. The electronic circuit is processed as test frame after detecting the length of the frame, when a test mode is selected. Independent claims are also included for the following: (A) a computer program product having instructions for executing a process of decoding bi-phase asynchronous frame (B) a storage unit having instructions executable by a computer for implementing a process of decoding bi-phase asynchronous frame (C) a control device including an electronic circuit for decoding a bi-phase asynchronous frame. L'invention concerne un circuit électronique de décodage d'un signal de données asynchrone biphasé.Selon l'invention, un tel circuit électronique comprend des moyens de génération d'une horloge de décodage mettant en oeuvre un compteur alimenté par une horloge interne, et répétant des cycles comprenant une incrémentation dudit compteur jusqu'à la détection d'une transition dans ledit signal de données, puis une décrémentation dudit compteur jusqu'à zéro.