DISPOSITIF D'ANTEMEMOIRE POUR UN PROCESSEUR DE SIGNAL NUMERIQUE ET PROCEDE DE COMMANDE
The device (100) has one cache memory (120) to activate the operation of a flag signal in response to a given interruption signal arising from the core of a digital signal processor (DSP). The memory (120) provides given number of instructions to the core and deactivates the flag signal operation. A...
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| Format: | Patent |
| Sprache: | fre |
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| Zusammenfassung: | The device (100) has one cache memory (120) to activate the operation of a flag signal in response to a given interruption signal arising from the core of a digital signal processor (DSP). The memory (120) provides given number of instructions to the core and deactivates the flag signal operation. Another cache memory (130) provides instruction to the core when the operation of the flag signal is deactivated. An Independent claim is also included for a process to control a cache memory device. |
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