DISPOSITIF DE MEMOIRE

The read only cache memory (4) stores long duration instructions (I) or instruction blocks (B). An extraction and transmission unit (6,7,11) selectively sends, as a function of address (A) contents, the instructions of instruction blocks from the cache memory to the processor (1). Processor (1) designed to transmit program addresses (A) to a memory consisting of a principal program memory (3, in which are stored instructions (I) or instructions blocks (B) for execution by the processor (1), and a dynamic cache memory (5) in which are stored instructions or instruction blocks whose use frequency during program execution has predetermined conditions. The memory also includes means for extracting and transmitting (8,9,10,12), as a function of the address (A) contents, selective extraction and transmission, from the principal (3) or cache memory (5) instructions or instruction blocks to be executed by the processor. Each instruction or instruction block stored in the principal memory is provided with a flag. The principal program memory (3) has an output (17) at which. during extraction of an instruction or instruction block, is presented with the associated flag state. The memory includes write control logic (16) which as a function of the flag state, writes or not, into a dynamic cache RAM memory (5) the instruction or instruction block extracted from the principal memory.