PROCEDE ET APPAREIL DE DEPHASAGE A ACTION RAPIDE, DESTINES A ETRE UTILISES DANS DES SYSTEMES D'ECHANTILLONNAGE NUMERIQUE

SELON CE PROCEDE ET CET APPAREIL PERMETTANT LE CONTROLE DE L'ECHANTILLONNAGE D'UN SIGNAL VIDEO COULEURS COMPOSITE ANALOGIQUE EN DES POSITIONS PRECISES PAR RAPPORT A LA PHASE DE LA SOUS-PORTEUSE COULEURS, UN DISPOSITIF 36 REALISE L'ECHANTILLONNAGE DU SIGNAL DE TELEVISION ET DES DISPOSITIFS 228, 230, FAISANT PARTIE D'UN DISPOSITIF 42 DELIVRANT DES SIGNAUX D'HORLOGE ET MEMORISANT LES SALVES DE REFERENCE, DELIVRENT UN SIGNAL D'HORLOGE DE SORTIE SYNCHRONISE EN PHASE AVEC LES ECHANTILLONS DE REFERENCE, TANDIS QU'UN DISPOSITIF 242 DETECTE TOUTE ERREUR DE PHASE DES ECHANTILLONS DE REFERENCE ET QU'UN DISPOSITIF 236 REGLE LA PHASE DU SIGNAL D'HORLOGE DE SORTIE DELIVRE.APPLICATION NOTAMMENT AUX APPAREILS D'ENREGISTREMENT ET DE REPRODUCTION MAGNETIQUES DE SIGNAUX DE TELEVISION. A method and apparatus is disclosed for controlling the sampling of a composite analog color video signal so that the analog signal is sampled at precise locations relative to the phase of the color subcarrier of the color video signal in the absence of modulation. The invention thereby enables a digitized signal having a constant phase relationship relative to the unmodulated subcarrier phase to be provided which can be advantageously used in magnetic recording and reproducing apparatus. Since the constancy of the location of the samples relative to the phase of the color burst is maintained prior to recording, there is no phase error that would pose a problem during reproducing of the signal. The apparatus stores a set of reference samples of a selected number of cycles of the color burst interval of the color video signal and generates an output clock signal that is phase synchronized with the reference samples, subsequently stores sets of comparison samples of color burst cycles from subsequent horizontal video lines using the generated clock signal and detects any error in the phase location thereof. The apparatus adjusts the phase of the generated output clock signal in response to any detected error signal and stores a new set of reference samples in the event that the error detected is beyond predetermined limits.