PROCEDE ET APPAREIL DE TRAITEMENT D'INFORMATION EN VUE NOTAMMENT DE L'ANALYSE SYNTAXIQUE
PROCEDE INFORMATIQUE DE TRAITEMENT D'UNE EXPRESSION CONSTITUEE PAR UNE SUCCESSION DE CARACTERES EN LANGAGE NUMERIQUE, DANS UN BUT D'ANALYSE SYNTAXIQUE DE RECONNAISSANCE, DE TRADUCTION OU ANALOGUE, SELON LEQUEL EN AYANT PREPARE UNE MEMOIRE A LIGNES D'INSTRUCTION EN FONCTION DU RESULTAT...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | fre |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROCEDE INFORMATIQUE DE TRAITEMENT D'UNE EXPRESSION CONSTITUEE PAR UNE SUCCESSION DE CARACTERES EN LANGAGE NUMERIQUE, DANS UN BUT D'ANALYSE SYNTAXIQUE DE RECONNAISSANCE, DE TRADUCTION OU ANALOGUE, SELON LEQUEL EN AYANT PREPARE UNE MEMOIRE A LIGNES D'INSTRUCTION EN FONCTION DU RESULTAT RECHERCHE, ON COMPARE CHAQUE CARACTERE DE L'EXPRESSION A UN CHAMP DE LIGNE D'INSTRUCTION CARACTERISTIQUE D'UN CARACTERE, ET ON REND OPERATOIRE UNE AUTRE LIGNE DE LA MEMOIRE D'INSTRUCTION EN FONCTION DU RESULTAT DE LA COMPARAISON.APPAREIL POUR LA MISE EN OEUVRE DE CE PROCEDE.
1. A module for processing an expression constituted by a succession of elements comprising digital characters for the purpose of syntax recognition analysis, translation, or the like, of the type comprising an input device (11) for presenting elements of the expression to be interrogated, a memory (19) comprising a plurality of instruction lines which are addressable by an addressing device (24) in correspondance with the interrogated elements of the input unit, each memory line comprising a field which corresponds to an instruction code and a field which corresponds to data relating to a reference element in connection with which the instruction is to be executed, a comparator (17) operating on the interrogated element under the control of the addressed instruction line, a control device (16), and a device (55) for outputting data as a function of the result of the comparison, characterized in that each memory line includes a field suitable for containing a reference element (262 ) and at least a first field and a second field (263 , 264 , 265 ) each for one address of an instruction line in the memory, in that a gate type switching device (42, 44, 46) is controlled by the control device (16) to connect the first field (264) or the second field (263 , 264 , 265 ) to the instruction memory addressing device (24) depending on whether the output from the comparator (17) is indicative of equality or inequality between the reference element (262 ) and the interrogated element in the input device (11), and in that each interrogated element in the input device (11) and each reference element in its respective instruction line field is a character. |
---|