PERFECTIONNEMENTS AUX DISPOSITIFS D'ADRESSAGE DE MEMOIRES
Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory.
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| Format: | Patent |
| Sprache: | fre |
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| Zusammenfassung: | Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. |
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