METHODE DE FABRICATION DE REGIONS DIELECTRIQUES DANS UN MATERIAU SEMI-CONDUCTEUR

1508719 Semiconductor devices ITT INDUSTRIES Inc 27 July 1976 [4 Aug 1975] 31226/76 Heading H1K Electrical isolation regions 50 of porous anodized semiconductor material, e.g. silicon, are provided in the semiconductor body of a device by removing dielectric layer 40 in selected regions to expose the body, and then electrolytically oxidizing the exposed regions by applying an anodizing potential in the body kept in an electrolyte, which is typically sulphuric, phosphoric, boric or nitric acid. N-type epitaxial layer 34 having graded impurity concentration may be chemically etched at the exposed regions prior to the anodic oxidation which is either a controlled one below the breakdown voltage of an anodic film initially formed and which results in preferred anodic oxidation, and thereby increased swelling, at the edges of openings in the dielectric layer 40 Fig. 10 (not shown), or is a rapid one caused by the application of a voltage high enough to break down the anodic film initially formed so as to convert the entire exposed region into a porous anodized material. The porous anodized material is hardened during subsequent heating steps involved in the diffusion of base and emitter regions 52, 54 respectively, which process step also results in the formation of an oxide film 64. P-type impurity may be diffused through the porous anodized silicon into the N-type epitaxial sub-layer (38) to form the regions 65 during the formation of the oxide film 64. Alternatively p-type impurity is introduced into the electrolyte during the anodization. Encapsulation of an integrated circuit comprising isolated transistors with individual external connections for the emitter, base and collector is described, Fig. 9 (not shown).