FOERFARANDE FOER VAEXLING AV OEVERFOERINGS- HASTIGHETEN I ETT MED TVENNE FRAON VARANDRA AVVIKANDE OEVERFOERINGSHASTIGHETER DRIVBART DATAOEVERFOERINGSSYSTEM
1. Method for reversing the transmission speed in a data transmission system which can be operated at one of two different transmission speeds (f1, f2), which comprises two interconnected data transmission devices (DS, DE), particularly modems, characterized in that the transition from the low trans...
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Format: | Patent |
Sprache: | fin ; swe |
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Zusammenfassung: | 1. Method for reversing the transmission speed in a data transmission system which can be operated at one of two different transmission speeds (f1, f2), which comprises two interconnected data transmission devices (DS, DE), particularly modems, characterized in that the transition from the low transmission speed (f1) to the high transmission speed (f2) occurs due to the fact that, following the interruption in the delivery of the data signals (DSf1) at the low transmission speed (f1), first a control character (S) and then, with the low transmission speed (f1), a scrambling bit sequence (M1f1) corresponding to a scrambling of a sequence of "1" or "0" bits, indicating the wish for changing the transmission speed, is delivered by the data transmission device (DS) transmitting the data signals, whereupon, following the acceptance of this control character (S) and the relevant scrambling bit sequence (M1f1), a corresponding control character (S) and a corresponding scrambling bit sequence (Q1f1) is transmitted back to the first-mentioned data transmission device (DS) by the data transmission device (DE) receiving the data signals as acknowledgement of its readiness to change the transmission speed, which firstmentioned data transmission device (DS) then sends out at the high transmission speed (f2) a corresponding scrambling bit sequence (E1f2) performing and indicating the adjustment of the high transmission speed in the transmitting data transmission device (DS) and requesting it in the receiving data transmitting device (DE), following the reception of which in the receiving data transmission device (DE), the latter sends back a corresponding scrambling bit sequence (Q1f2), which indicates its adjustment to the high transmission speed (f2) and the readiness for receiving data signals at the high transmission speed (f2), to the said transmitting data transmission device (DS) which thereupon sends out data signals (DSf2) to the receiving data transmission device (DE) at the said high transmission speed (f2), that the transition from the high transmission speed (f2) to the low transmission speed (f1) occurs due to the fact that, after interruption of the data signal transmission, first a control character (S) and then, with the low transmission speed (f1) a scrambling bit sequence (M0f1) corresponding to the scrambling of the sequence of "0" or "1" bits, which indicates the wish for changing the transmission speed, is delivered to the receiving data transmissi |
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