PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES. (Machine-translation by Google Translate, not legally binding)
A process for creating bipolar and CMOS transistors on a p-type silicon substrate. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks (51, 52, 53) of material are created over the gate element...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng ; spa |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A process for creating bipolar and CMOS transistors on a p-type silicon substrate. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks (51, 52, 53) of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer (17) in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer (32) in contact with the epitaxial layer. Walls (61) of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon (81) in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes. (Machine-translation by Google Translate, not legally binding)
UN PROCEDIMIENTO PARA FABRICAR TRANSISTORES BIPOLARES Y CMOS SOBRE UN SUSTRATO DE SILICIO DEL TIPO P-. EL SUSTRATO DE SILICIO TIENE LOS POZOS ENTERRADOS N+ HABITUALES Y REGIONES DE OXIDO DE CAMPO PARA AISLAR LOS DISPOSITIVOS TRANSISTORES INDIVIDUALES. DE ACUERDO CON EL PROCEDIMIENTO, SE CREAN PILAS DE MATERIAL SOBRE LOS ELEMENTOS DE PUERTA DE LOS DISPOSITIVOS CMOS Y SOBRE LOS ELEMENTOS EMISORES DE LOS TRANSISTORES BIPOLARES. LAS PILAS DE MATERIAL SOBRE LOS ELEMENTOS DE PUERTA TIENEN UNA CAPA DE PUERTA DE DIOXIDO DE SILICIO EN CONTACTO CON LA CAPA EPITAXIAL DEL SUSTRATO Y LAS PILAS DE MATERIAL, SOBRE LOS ELEMENTOS EMISORES, TIENEN UNA CAPA DE SILICIO POLICRISTALINO EN CONTACTO CON LA CAPA EPITAXIAL. SE CREAN PAREDES DE DIOXIDO DE SILICIO ALREDEDOR DE LAS PILAS CON EL FIN DE AISLAR EL MATERIAL DENTRO DE LAS PILAS DEL MATERIAL DEPOSITADO FUERA DE LAS PAREDES. FUERA DE LAS PAREDES QUE RODEAN A LAS PILAS, SE DEPOSITA SILICIO POLICRISTALINO EN CONTACTO CON LA CAPA EPITAXIAL. TODAS LAS CAPAS DE SILICIO POLICRISTALINO EN CONTACTO CON LA |
---|