STAGGERED VIA ARCHITECTURE ACROSS UNIT CELLS

Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.