MULTIPLY-ACCUMULATOR ARRAY CIRCUIT WITH ACTIVATION CACHE

MULTIPLY-ACCUMULATOR ARRAY CIRCUIT WITH ACTIVATION CACHE

Embodiments of the present disclosure include a multiply-accumulator (MAC) array circuit comprising an activation cache and a plurality of multiply-accumulator (MA) groups. The activation cache comprises cache lines configured to store sub-slices of an input activation array. The cache lines are cou...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: AVUDAIYAPPAN, Karthikeyan, ANDREWS, Jeffrey A
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Embodiments of the present disclosure include a multiply-accumulator (MAC) array circuit comprising an activation cache and a plurality of multiply-accumulator (MA) groups. The activation cache comprises cache lines configured to store sub-slices of an input activation array. The cache lines are coupled to particular MA groups. Activations stored in the cache lines may be used and reused across multiple MA groups.