SENSE AMPLIFIER CIRCUIT, CORRESPONDING MEMORY DEVICE AND METHOD OF OPERATION

In a sense amplifier circuit (40) for a memory device, first (304L) and second (304R) input terminals are coupled to first (302L) and second (302R) memory sensing nodes, respectively. A comparator circuit (42) has first (402L) and second (402R) input nodes as well as first (306L) and second (306R) output nodes configured to produce first (IL(t)) and second (IR(t)) output currents, respectively. A first input transistor (MPCL) has a conductive channel arranged between the first comparator input node and the first comparator output node, and a control terminal coupled to an internal biasing node (COMPINT). A second input transistor (MPCR) has a conductive channel arranged between the second comparator input node and the second comparator output node, and a control terminal coupled to the internal biasing node (COMPINT). The first and second comparator input nodes are selectively couplable to each other, in response to a compensation signal (SA_CONNECT_BL) being asserted, or to the first and second input terminals, respectively, in response to the compensation signal being de-asserted. The internal biasing node is selectively couplable to a comparator biasing node (BIASPCOMP) in response to a bias enable signal (SA_ENAB_BL) being asserted, or is floating in response to the bias enable signal being de-asserted. A sensing circuit (44, 46) is coupled to the comparator output nodes (306L, 306R) and produces a memory reading signal (SA_OUT) as a function of a difference between the first and second output currents.