SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a bit line (BL) extending in a first direction (D1), an active pattern (AP) on the bit line, the active pattern including first and second vertical portions (VP1, VP2) facing each other in the first direction and a horizontal portion (HP) connecting the first and second vertical portions, first and second word lines (WL1, WL2) on the horizontal portion between the first and second vertical portions, the first and second word lines extending in a second direction (D2) crossing the first direction, a gate insulating pattern (GIL1, GIL2) between the first and second word lines and the active pattern, and a capacitor (CAP) connected to each of the first and second vertical portions, the capacitor including a first electrode pattern (EP1) connected to one of the first and second vertical portions, a second electrode pattern (EP2) on the first electrode pattern, and a ferroelectric pattern (CIL) between the first electrode pattern and the second electrode pattern.