REDUCED POWER CONSUMPTION CIRCUIT AND CORRESPONDING METHOD

A system on chip, SOC circuit comprising a plurality of peripherals (1811, 1812, ..., 181k; ...; 18N1, 18N2, ..., 18Nk) configured to be clocked with respective clock signals (CK11, CK12, ..., CK1k; ..., CKN1, CKN2, ..., CKNk), wherein the circuit comprises a clock controller (217) configured (161, ..., 16N; 191, ..., 19N) to produce said respective clock signals (CK11, CK12, ..., CK1k; ..., CKN1, CKN2, ..., CKNk) via respective clock divide factors (N1, ..., Nk), the clock controller (217) comprising a plurality of storage locations having stored therein respective sets of clock divide factors (N1, ..., Nk), wherein the clock controller (217) comprises clock divide factor selection circuitry (266) configured to select an operating set of clock divide factors (N1, ..., Nk) out of said respective sets of clock divide factors (N1, ..., Nk) stored in said plurality of storage locations and wherein the clock controller (217) is configured (161, ..., 16N; 191, ..., 19N) to apply to the plurality of peripherals (1811, 1812, ..., 181k; ...; 18N1, 18N2, ..., 18Nk) respective clock signals (CK11, CK12, ..., CK1k; ..., CKN1, CKN2, ..., CKNk) produced via the clock divide factors (N1, ..., Nk) in the operating set of clock divide factors (N1, ..., Nk) selected out of said respective sets of clock divide factors (N1, ..., Nk) stored in said plurality of storage locations.