POWER SEMICONDUCTOR MODULE ARRANGEMENT

A power semiconductor module arrangement comprises a substrate (10) comprising a dielectric insulation layer (11), and a first metallization layer (111) arranged on a first surface of the dielectric insulation layer (11), at least one semiconductor body (20) arranged on and attached to the first metallization layer (111) by means of an electrically conductive connection layer (30), and at least one electrically conducting element (80) arranged on the first metallization layer (111), wherein the first metallization layer (111) is a structured layer comprising a plurality of different subsections, the first metallization layer (111) has a uniform thickness in a vertical direction (y), wherein the vertical direction (y) is perpendicular to the first surface of the dielectric insulation layer (11), each of the at least one electrically conducting element (80) is arranged on and covers a subarea of a sub-section, thereby increasing the cross-sectional area of the subarea of the respective sub-section, and each of the at least one electrically conducting element (80) comprises an electrically conductive connection layer (30) without a semiconductor body (20) arranged thereon.