3D-STACKED TRANSISTOR DEVICE WITH BARRIER LAYER BETWEEN UPPER GATE STRUCTURE AND LOWER GATE STRUCTURE

3D-STACKED TRANSISTOR DEVICE WITH BARRIER LAYER BETWEEN UPPER GATE STRUCTURE AND LOWER GATE STRUCTURE

Provided is a three-dimensionally-stacked field-effect transistor, 3DSFET, device including a plurality of 3DSFET structures on a single substrate, wherein each of the 3DSFET structures includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SEO, Kang-ill, BAEK, Jaejik, YUN, Seungchan
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Provided is a three-dimensionally-stacked field-effect transistor, 3DSFET, device including a plurality of 3DSFET structures on a single substrate, wherein each of the 3DSFET structures includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.