CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE

CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE

A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integr...

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1. Verfasser: Wu, Zhuojie
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Sprache:eng ; fre ; ger
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
OPTICS
PHYSICS
SEMICONDUCTOR DEVICES
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creator Wu, Zhuojie
description A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4400885A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4400885A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4400885A13</originalsourceid><addsrcrecordid>eNqNjb0KwjAUhbM4iPoO9wWEihW6xuSmCZgfbhMcS5E4iVbq-2MqLm5OH4fzcc6SPYU2AbpIScRECGcTNVhvuk86ciKDBPzkXQs-oDOFxgHKFiFqJPQKuJNguUuKzxuzYTFqL6F0xYHfizVbXIfblDdfrhgojEJv8_jo8zQOl3zPrx5DXVdV0xz4bv-H8gaqADe3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE</title><source>esp@cenet</source><creator>Wu, Zhuojie</creator><creatorcontrib>Wu, Zhuojie</creatorcontrib><description>A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS ; OPTICS ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240717&amp;DB=EPODOC&amp;CC=EP&amp;NR=4400885A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240717&amp;DB=EPODOC&amp;CC=EP&amp;NR=4400885A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Wu, Zhuojie</creatorcontrib><title>CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE</title><description>A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</subject><subject>OPTICS</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjb0KwjAUhbM4iPoO9wWEihW6xuSmCZgfbhMcS5E4iVbq-2MqLm5OH4fzcc6SPYU2AbpIScRECGcTNVhvuk86ciKDBPzkXQs-oDOFxgHKFiFqJPQKuJNguUuKzxuzYTFqL6F0xYHfizVbXIfblDdfrhgojEJv8_jo8zQOl3zPrx5DXVdV0xz4bv-H8gaqADe3</recordid><startdate>20240717</startdate><enddate>20240717</enddate><creator>Wu, Zhuojie</creator><scope>EVB</scope></search><sort><creationdate>20240717</creationdate><title>CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE</title><author>Wu, Zhuojie</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4400885A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</topic><topic>OPTICS</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Wu, Zhuojie</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wu, Zhuojie</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE</title><date>2024-07-17</date><risdate>2024</risdate><abstract>A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
OPTICS
PHYSICS
SEMICONDUCTOR DEVICES
title CHIP STRUCTURE WITH MOISTURE BARRIER ALONG OPENING IN EDGE THEREOF AND MANUFACTURING METHOD OF THE CHIP STRUCTURE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T21%3A13%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Wu,%20Zhuojie&rft.date=2024-07-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4400885A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true