SCALABLE SYSTEM ON A CHIP

SCALABLE SYSTEM ON A CHIP

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system inc...

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Bibliographische Detailangaben
Hauptverfasser: SRIDHARAN, Srinivasa Rangan, VASH, James, TAMARI, Eran, FISHWICK, Steven, KUZI, Tal, REDSHAW, Jonathan M, GONION, Jeffry E, LEVY-RUBIN, Lital, KOLOR, Sergio, HAMMARLUND, Per H, LESHEM, Nir, WILLIAMS, Gerard R. III, LAHAV, Sagi, FUKAMI, Shawn M, HUTSELL, Steven R, PILIP, Mark, KAUSHIKKAR, Harshavardhan, GUNNA, Ramesch B, GARG, Gaurav, TUCKER, Charles E, TOTA, Sergio V, ZIMET, Lior, DAVIDOV, Dany
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.