MEMORY DEVICE INCLUDING STACKED PASS TRANSISTORS

A memory device including a memory block including a plurality of wordlines stacked in a vertical direction and extending in a first horizontal direction; and a pass transistor block including a plurality of pass transistors stacked in the vertical direction, wherein the plurality of pass transistors are configured to transmit a plurality of driving signals respectively to the plurality of wordlines, wherein each pass transistor of the plurality of pass transistors includes: a body region having an upper surface and a lower surface which face in the vertical direction, a first side surface and a second side surface which face in the first horizontal direction, and a front surface and a rear surface which face in a second horizontal direction; a first source-drain electrode on the first side surface, and configured to receive a corresponding driving signal of the plurality of driving signals; a second source-drain electrode on the second side surface, wherein the second source-drain electrode is electrically connected to a side surface of a corresponding wordline of the plurality of wordlines; and a first vertical gate electrode on a first surface from among the front surface and the rear surface.