SCALABLE SYSTEM ON A CHIP

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system inc...

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Bibliographische Detailangaben
Hauptverfasser:	SRIDHARAN, Srinivasa, Rangan, VASH, James, TAMARI, Eran, FISHWICK, Steven, KUZI, Tal, FUKAMI, Shawn, M, LEVY-RUBIN, Lital, HAMMARLUND, Per, H, KOLOR, Sergio, GUNNA, Ramesh, B, WILLIAMS, III, Gerard, R, LESHEM, Nir, LAHAV, Sagi, HUTSELL, Steven, R, PILIP, Mark, GONION, Jeffry, E, KAUSHIKKAR, Harshavardhan, GARG, Gaurav, TUCKER, Charles, E, TOTA, Sergio, V, ZIMET, Lior, REDSHAW, Jonathan, M, DAVIDOV, Dany
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.